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connection diagrams a AD745 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 ultralow noise, high speed, bifet op amp product description the AD745 is an ultralow noise, high speed, fet input operational amplifier. it offers both the ultralow voltage noise and high speed generally associated with bipolar input op amps and the very low input currents of fet input devices. its 20 mhz bandwidth and 12.5 v/ m s slew rate makes the AD745 an ideal amplifier for high speed applications demanding low noise and high dc precision. furthermore, the AD745 does not exhibit an output phase reversal. rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ? w resistor noise only r source r source o e input noise voltage ?nv/ hz (??? ( ) AD745 & resistor or op37 & resistor op37 & resistor ( ?) AD745 + resistor the AD745s guaranteed, tested maximum input voltage noise of 4 nv/ ? hz at 10 khz is unsurpassed for a fet-input mono- lithic op amp, as is its maximum 1.0 m v p-p noise in a 0.1 hz to 10 hz bandwidth. the AD745 also has excellent dc perfor- mance with 250 pa maximum input bias current and 0.5 mv maximum offset voltage. the internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. this makes the AD745 especially useful as a preamplifier where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. the AD745 is available in five performance grades. the AD745j and AD745k are rated over the commercial temperature range of 0 c to +70 c. the AD745a and AD745b are rated over the industrial temperature range of C40 c to +85 c. the AD745s is rated over the military temperature range of C55 c to +125 c and is available processed to mil-std-883b, rev. c. the AD745 is available in 8-pin plastic mini-dip, 8-pin cerdip, 16-pin soic, or in chip form. frequency ?hz open-loop gain ?db phase margin ?degrees 120 100 80 60 40 20 0 ?0 100 1k 10k 100k 1m 10m 100m 120 100 80 60 40 20 0 ?0 phase gain features ultralow noise performance 2.9 nv/ ? hz at 10 khz 0.38 m v p-p, 0.1 hz to 10 hz 6.9 fa/ ? hz current noise at 1 khz excellent ac performance 12.5 v/ m s slew rate 20 mhz gain bandwidth product thd = 0.0002% @ 1 khz internally compensated for gains of +5 (or C4) or greater excellent dc performance 0.5 mv max offset voltage 250 pa max input bias current 2000 v/mv min open loop gain available in tape and reel in accordance with eia-481a standard applications sonar photodiode and ir detector amplifiers accelerometers low noise preamplifiers high performance audio 16-pin soic (r) package offset null 1 2 3 4 5 6 7 8 AD745 top view nc output offset null ?in +in +v s ? s nc = no connect 1 2 3 4 5 6 7 89 10 11 12 13 14 16 15 AD745 top view nc nc nc nc nc nc nc nc nc offset null ?in +in output offset null ? s +v s 8-pin plastic mini-dip (n) & 8-pin cerdip (q) packages
AD745Cspecifications (@ +25 8 c and 6 15 v dc, unless otherwise noted) model AD745j/a conditions min typ max units input offset voltage 1 initial offset 0.25 1.0/0.8 mv initial offset t min to t max 1.5 mv vs. temp. t min to t max 2 m v/ c vs. supply (psrr) 12 v to 18 v 2 90 96 db vs. supply (psrr) t min to t max 88 db input bias current 3 either input v cm = 0 v 150 400 pa either input @ t max v cm = 0 v 8.8/25.6 na either input v cm = +10 v 250 600 pa either input, v s = 5 v v cm = 0 v 30 200 pa input offset current v cm = 0 v 40 150 pa offset current @ t max v cm = 0 v 2.2/6.4 na frequency response gain bw, small signal g = C4 20 mhz full power response v o = 20 v p-p 120 khz slew rate g = C4 12.5 v/ m s settling time to 0.01% 5 m s total harmonic f = 1 khz distortion 4 g = C4 0.0002 % input impedance differential 1 10 10 i 20 w i pf common mode 3 10 11 i 18 w i pf input voltage range differential 5 20 v common-mode voltage +13.3, C10.7 v over max operating range 6 C10 +12 v common-mode rejection ratio v cm = 10 v 80 95 db t min to t max 78 db input voltage noise 0.1 to 10 hz 0.38 m v p-p f = 10 hz 5.5 nv/ ? hz f = 100 hz 3.6 nv/ ? hz f = 1 khz 3.2 5.0 nv/ ? hz f = 10 khz 2.9 4.0 nv/ ? hz input current noise f = 1 khz 6.9 fa/ ? hz open loop gain v o = 10 v r load 3 2 k w 1000 4000 v/mv t min to t max 800 v/mv r load = 600 w 1200 v/mv output characteristics voltage r load 3 600 w +13, C12 v r load 3 600 w +13.6, C12.6 v t min to t max +12, C10 v r load 3 2 k w 12 +13.8, C13.1 v current short circuit 20 40 ma power supply rated performance 15 v operating range 4.8 18 v quiescent current 8 10.0 ma transistor count # of transistors 50 notes 1 input offset voltage specifications are guaranteed after 5 minutes of operations at t a = +25 c. 2 test conditions: +v s = 15 v, Cv s = 12 v to 18 v and +v s = 12 v to +18 v, Cv s = 15 v. 3 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperature, the current doubles every 10 c. 4 gain = C4, r l = 2 k w , c l = 10 pf. 5 defined as voltagc between inputs, such that neither exceeds 10 v from common. 6 the AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. all min and max specifications are guaranteed. specifications subject to change without notice. rev. c C2C
AD745 rev. c C3C ordering guide package model temperature range option* AD745jn 0 c to +70 c n-8 AD745an C40 c to +85 c n-8 AD745jr-16 0 c to +70 c r-16 *n = plastic dip; r = small outline ic. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 w soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short-circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (q) . . . . . . . . . C65 c to +150 c storage temperature range (n, r) . . . . . . . C65 c to +125 c operating temperature range AD745j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c AD745a/b . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD745s . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-pin plastic package: q ja = 100 c/w, q jc = 50 c/w 8-pin cerdip package: q ja = 110 c/w, q jc = 30 c/w 8-pin plastic soic package: q ja = 100 c/w, q jc = 30 c/w esd susceptibility an esd classification per method 3015.6 of mil-std-883c has been performed on the AD745, which is a class 1 device. using an imcs 5000 automated esd tester, the two null pins will pass at voltages up to 1000 volts, while all other pins will pass at voltages exceeding 2500 volts. metalization photograph dimensions shown in inches and (mm).
AD745 rev. c C4C Ctypical characteristics (@ + 25 8 c, v s = 6 15 v unless otherwise noted) 0 5 10 15 20 0 5 10 15 20 input voltage swing ?volts r = 10k w ? in +v in load supply voltage volts + figure 1. input voltage swing vs. supply voltage 0 510 15 20 6 12 9 3 0 quiescent current ?ma supply voltage volts figure 4. quiescent current vs. supply voltage 0 ?2 12 common-mode voltage ?volts ? ? ? 3 6 9 input bias current ?pa 300 200 100 0 figure 7. input bias current vs. common-mode voltage 10 100 1k 10k load resistance ? w 5 10 15 20 25 30 35 0 output voltage swing ?volts p-p figure 3. output voltage swing vs. load resistance 200 100 10 1 0.1 0.01 10k 100k 1m 10m 100m frequency ?hz output impedance ? w closed-loop gain = ? figure 6. output impedance vs. frequency 28 26 24 22 20 18 16 14 ?0 ?0 ?0 0 20 40 60 80 100 120 140 gain bandwidth product ?mhz temperature ? c figure 9. gain bandwidth product vs. temperature 0 5101520 20 5 10 15 0 output voltage swing ?volts r = 10k w positive supply negative supply load supply voltage volts + figure 2. output voltage swing vs. supply voltage ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature ? c 10 ? 10 ? 10 ? 10 ? ?0 10 ?1 10 10 ?2 input bias current ?amps figure 5. input bias current vs. temperature ?60 ?40 ?20 0 20 40 60 80 100 120 140 0 40 30 20 10 50 60 70 80 current limit ?ma temperature ? c + output current ?output current figure 8. short circuit current limit vs. temperature
AD745 rev. c C5C frequency ?hz open-loop gain ?db phase margin ?degrees 120 100 80 60 40 20 0 ?0 100 1k 10k 100k 1m 10m 100m 120 100 80 60 40 20 0 ?0 phase gain figure 10. open-loop gain and phase vs. frequency 120 110 100 90 80 70 60 50 1k 10k 100k 1m 10m 100 vcm = 10v common-mode rejection ?db frequency ?hz figure 13. common-mode rejection vs. frequency ?0 ?0 ?00 ?40 ?20 ?0 10 100 1k 10k 100k frequency ?hz total harmonic distortion (thd) ?db total harmonic distortion (thd) ?% 0.00001 0.0001 0.001 0.01 0.1 1.0 gain = +10 gain = +100 gain = ? figure 16. total harmonic distortion vs. frequency 14 12 10 8 ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature ? c slew rate ?volts/ m s closed-loop gain = +5 figure 11. slew rate vs. temperature frequency ?hz 120 100 80 60 40 20 0 100 1k 10k 100k 1m 10m 100m power supply rejection ?db + supply ?supply figure 14. power supply rejection vs. frequency closed-loop gain = +5 100 10 1.0 0.1 10 100 1k 10k 100k 1m 10m frequency ?hz noise voltage (reffered to input) ?nv/ hz figure 17. input noise voltage spectral density 05 10 15 20 80 120 130 140 150 100 open-loop gain ?db supply voltage volts rl = 2k w figure 12. open-loop gain vs. supply voltage 10k 100k 1m 10m frequency ?hz 35 30 25 20 15 10 5 0 output voltage ?volts p-p r = 2k w l figure 15. large signal frequency response 1.0 10 100 1k 100 1k 10k 100k 10 1 frequency ?hz current noise spectral density ?fa/ hz figure 18. input noise current spectral density typical characteristicsC
AD745 rev. c C6C Ctypical characteristics 72 0 15 18 6 ?0 12 ?5 36 24 30 42 48 54 66 60 10 5 0 ? number of units input offset voltage drift ? m v/ c o total units = 760 figure 19. distribution of offset voltage drift. t a = +25 c to +125 c AD745 0.1 m f 2 3 7 6 4 0.1 m f +v s ? s 10pf 20pf 2k w 499 w square wave input v in v out c l figure 22a. gain of 5 follower, 8-pin package pinout AD745 0.1 m f 2 3 7 6 4 0.1 m f +v s ? s 10pf 499 w square wave input v in v out c l 20pf 2k w figure 23a. gain of 4 inverter, 8-pin package pinout 648 594 540 486 432 378 324 270 216 162 108 54 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 2.6 number of units input voltage noise @ 10khz ?nv/ ? hz 0 total units = 4100 figure 20. typical input noise voltage distribution @ 10 khz 2 m s 10 90 100 5v 0% figure 22b. gain of 5 follower large signal pulse response 2 m s 10 90 100 5v 0% figure 23b. gain of 4 inverter large signal pulse response AD745 v adjust os 1 m f 0.1 m f 2 3 7 6 5 1 4 2m w 1m w 0.1 m f 1 m f +v s ? s + + figure 21. offset null configuration, 8-pin package pinout 500ns 10 90 100 50mv 0% figure 22c. gain of 5 follower small signal pulse response 500ns 10 90 100 50mv 0% figure 23c. gain of 4 inverter small signal pulse response
AD745 rev. c C7C op amp performance jfet vs. bipolar the AD745 offers the low input voltage noise of an industry standard bipolar op amp without its inherent input current errors. this is demonstrated in figure 24, which compares input voltage noise vs. input source resistance of the op37 and the AD745 op amps. from this figure, it is clear that at high source impedance the low current noise of the AD745 also provides lower total noise. it is also important to note that with the AD745 this noise reduction extends all the way down to low source impedances. the lower dc current errors of the AD745 also reduce errors due to offset and drift at high source impedances (figure 25). the internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. this makes the AD745 especially useful as a preamplifier, where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ? w op37 & resistor AD745 + resistor resistor noise only AD745 & resistor or op37 & resistor r source r source o e input noise voltage ?nv/ hz ( ) (??? ( ?) figure 24. total input noise spectral density @ 1 khz vs. source resistance source resistance ? w adop37g AD745 kn input offset voltage ?mv 100 10 1.0 0.1 100 1k 10k 100k 1m 10m figure 25. input offset voltage vs. source resistance designing circuits for low noise an op amps input voltage noise performance is typically divided into two regions: flatband and low frequency noise. the AD745 offers excellent performance with respect to both. the figure of 2.9 nv/ ? hz @ 10 khz is excellent for a jfet input amplifier. the 0.1 hz to 10 hz noise is typically 0.38 m v p-p. the user should pay careful attention to several design details in order to optimize low frequency noise performance. random air currents can generate varying thermocouple voltages that appear as low frequency noise: therefore sensitive circuitry should be well shielded from air flow. keeping absolute chip temperature low also reduces low frequency noise in two ways: first, the low freq uency noise is strongly dependent on the ambient tempera ture and increases above +25 c. secondly, since the gradient of temperature from the ic package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. low frequency current noise can be computed from the magnitude of the dc bias current ~ i n = 2 qi b d f ? ? ? and increases below approximately 100 hz with a 1/f power spectral density. for the AD745 the typical value of current noise is 6.9 fa/ ? hz at 1 khz. using the formula, i ~ n = 4 kt / r d f , to compute the johnson noise of a resistor, expressed as a current, one can see that the current noise of the AD745 is equivalent to that of a 3.45 10 8 w source resistance. at high frequencies, the current noise of a fet increases proportionately to frequency. this noise is due to the real part of the gate input impedance, which decreases with frequency. this noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude. in any fet input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. this noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pf in value. low noise charge amplifiers as stated, the AD745 provides both low voltage and low current noise. this combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. when dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise. charge (q) is related to voltage and current by the simply stated fundamental relationships: q = cv and i = dq dt as shown, voltage, current and charge noise can all be directly related. the change in open circuit voltage ( d v) on a capacitor will equal the combination of the change in charge ( d q/c) and the change in capacitance with a built-in charge (q/ d c).
AD745 rev. c C8C figure 28 shows that these two circuits have an identical frequency response and the same noise performance (provided that c s /c f = r1/ r2). one feature of the first circuit is that a t network is used to increase the effective resistance of r b and improve the low frequency cutoff point by the same factor. decibels referenced to 1v/ ?00 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?00 ?10 ?20 0.01 0.1 1 10 100 1k 10k 100k frequency ?hz total output noise noise due to r alone b noise due to i alone b hz figure 28. noise at the outputs of the circuits of figures 26 and 27. gain = 10, c s = 3000 pf, r b = 22 m w however, this does not change the noise contribution of r b which, in this example, dominates at low frequencies. the graph of figure 29 shows how to select an r b large enough to minimize this resistors contribution to overall circuit noise. when the equivalent current noise of r b (( ? 4 kt )/r) equals the noise of i b 2 qi b () , there is diminishing return in making r b larger. 1pa 10pa 100pa 1na 10na 5.2 x 10 10 5.2 x 10 9 5.2 x 10 8 5.2 x 10 7 5.2 x 10 6 input bias current resistance in w figure 29. graph of resistance vs. input bias current where the equivalent noise ? 4 kt/r , equals the noise of the bias current i b 2 qi b () to maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. this is represented by the optional resistor r b in figures 26 and 27. as previously mentioned, for best noise performance care should be taken to also balance the source capacitance designated by c b the value for c b in figure 26 would be equal to c s in figure 27. at values of c b over 300 pf, there is a diminishing impact on noise; capacitor c b can then be simply a large mylar bypass capacitor of 0.01 m f or greater. figures 26 and 27 show two ways to buffer and amplify the output of a charge output transducer. both require using an amplifier which has a very high input impedance, such as the AD745. figure 26 shows a model of a charge amplifier circuit. here, amplification depends on the principle of conservation of charge at the input of amplifier a1, which requires that the charge on capacitor c s be transferred to capacitor c f , thus yielding an output voltage of d q/c f . the amplifiers input voltage noise will appear at the output amplified by the noise gain (1 + (c s /c f )) of the circuit. c f r b c s r 2 r1 a1 c s c f = * c b r b * r1 r2 figure 26. a charge amplifier circuit r1 r b * c * a2 c s r b r2 *optional, see text b figure 27. model for a high z follower with gain the second circuit, figure 27, is simply a high impedance follower with gain. here the noise gain (1 + (r1/r2)) is the same as the gain from the transducer to the output. resistor r b , in both circuits, is required as a dc bias current return. there are three important sources of noise in these circuits. amplifiers a1 and a2 contribute both voltage and current noise, while resistor r b contributes a current noise of: ~ n = 4 k t r b d f where: k = boltzmans constant = 1.381 10 C23 joules/kelvin t = absolute temperature, kelvin (0 c = +273.2 kelvin) d f = bandwidth C in hz (assuming an ideal brick wall filter) this must be root-sum-squared with the amplifiers own current noise.
AD745 rev. c C9C how chip package type and power dissipation affect input bias current as with all jfet input amplifiers, the input bias current of the AD745 is a direct function of device junction temperature, i b approximately doubling every 10 c. figure 30 shows the relationship between bias current and junction temperature for the AD745. this graph shows that lowering the junction temperature will dramatically improve i b . ?0 ?0 ?0 0 20 40 60 80 100 120 140 ?1 ?0 10 ? 10 ? 10 ? 10 ? 10 10 10 ?2 input bias current ?amps junction temperature ? c v = 15v t = +25 c s a + - figure 30. input bias current vs. junction temperature the dc thermal properties of an ic can be closely approximated by using the simple model of figure 31 where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance ( q in c/watt). = device dissipation = ambient temperature = junction temperature = thermal resistance ?junction to case = thermal resistance ?case to ambient p in t j t a where: ca q jc q p in t a t j jc q ca q ja q figure 31. device thermal model from this model t j = t a + q ja p in . therefore, i b can be determined in a particular application by using figure 30 together with the published data for q ja and power dissipation. the user can modify q ja by use of an appropriate clip-on heat sink such as the aavid #5801. q ja is also a variable when using the AD745 in chip form. figure 32 shows bias current vs. supply voltage with q ja as the third variable. this graph can be used to predict bias current after q ja has been computed. again bias current will double for every 10 c. the designer using the AD745 in chip form (figure 33) must also be concerned with both q jc and q ca , since q jc can be affected by the type of die mount technology used. typically, q jc s will be in the 3 c to 5 c/watt range; therefore, for normal packages, this small power dissipation level may be ignored. but, with a large hybrid substrate, q jc will dominate proportionately more of the total q ja . 300 0 100 200 t = +25 c a input bias current ?pa supply voltage ? volts = 165 c/w q q q ja ja ja = 0 c/w = 115 c/w 5 10 15 figure 32. input bias current vs. supply voltage for various values of q ja q q j t t a (j to die mount) (die mount to case) case a b q q q ab jc + = figure 33. breakdown of various package thermal resistance reduced power supply operation for lower i b reduced power supply operation lowers i b in two ways: first, by lowering both the total power dissipation and, second, by reducing the basic gate-to-junction leakage (figure 32). figure 34 shows a 40 db gain piezoelectric transducer amplifier, which operates without an ac coupling capacitor, over the C40 c to +85 c temperature range. if the optional coupling capacitor, c1, is used, this circuit will operate over the entire C55 c to +125 c temperature range. 100 w 10k w c1* ct** transducer +5v ?v *optional dc blocking capacitor **optional, see text 10 w 8 10 w 8 ** AD745 c t figure 34. a piezoelectric transducer
AD745 rev. c C10C two high performance accelerometer amplifiers two of the most popular charge-out transducers are hydro- phones and accelerometers. precision accelerometers are typi- cally calibrated for a charge output (pc/g).* figures 35a and 35b show two ways in which to configure the AD745 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. the input sensitivity of these circuits will be de- termined by the value of capacitor c1 and is equal to: d v out = d q out c 1 the ratio of capacitor c1 to the internal capacitance (c t ) of the transducer determines the noise gain of this circuit (1 + c t /c1). the amplifiers voltage noise will appear at its output amplified by this amount. the low frequency bandwidth of these circuits will be dependent on the value of resistor r1. if a t network is used, the effective value is: r1 (1 + r2/r3). *pc = picocoulombs g = earths gravitational constant AD745 b&k model 4370 or equivalent 1250pf c1 r1 r2 9k w 110m w (5x22m w ) 1k w r3 output 0.8mv/pc figure 35a. a basic accelerometer circuit b&k model 4370 or equivalent 1250pf c1 r1 r2 9k w 110m w (5x22m w ) 1k w r3 output = 0.8mv/pc ad711 c2 2.2 m f 18m w r4 r5 c3 18m w 2.2 m f *pc = picocoulombs g = earth's gravitational constant AD745 figure 35b. an accelerometer circuit employing a dc servo amplifier a dc servo loop (figure 35b) can be used to assure a dc output <10 mv, without the need for a large compensating resistor when dealing with bias currents as large as 100 na. for optimal low frequency performance, the time constant of the servo loop (r4c2 = r5c3) should be: time constant 3 10 r 11 + r 2 r 3 ? ? ? ? c 1 a low noise hydrophone amplifier hydrophones are usually calibrated in the voltage-out mode. the circuit of figures 36a can be used to amplify the output of a typical hydrophone. if the optional ac coupling capacitor c c is used, the circuit will have a low frequency cutoff determined by an rc time constant equal to: time constant = 1 2 p c c 100 w where the dc gain is 1 and the gain above the low frequency cutoff (1/(2 p c c (100 w ))) is equal to (1 + r2/r3). the circuit of figure 36b uses a dc servo loop to keep the dc output at 0 v and to maintain full dynamic range for i b s up to 100 na. the time constant of r7 and c1 should be larger than that of r1 and c t for a smooth low frequency response. 100 w 1900 w r3 c1* *optional, see text ** 1 volt per micropascal 10 w 8 AD745 c t r2 r4* r1 b&k type 8100 hydrophone input sensitivity = ?79db re. 1v/ m pa** output c c figure 36a. a low noise hydrophone amplifier the transducer shown has a source capacitance of 7500 pf. for smaller transducer capacitances ( 300 pf), lowest noise can be achieved by adding a parallel rc network (r4 = r1, c1 = c t ) in series with the inverting input of the AD745. 100 w 1900 w r3 c1* *optional, see text 10 w 8 AD745 c t r2 r4* ad711k r1 output b&k type 8100 hydrophone r6 1m w r5 100k w 16m w c2 0.27 m f 16m w r4 10 w 8 dc output 1mv for i (AD745) 100na b figure 36b. a hydrophone amplifier incorporating a dc servo loop
AD745 rev. c C11C design considerations for i-to-v converters there are some simple rules of thumb when designing an i-v converter where there is significant source capacitance (as with a photodiode) and bandwidth needs to be optimized. consider the circuit of figure 37. the high frequency noise gain (1 + c s /c l ) is usually greater than five, so the AD745, with its higher slew rate and bandwidth is ideally suited to this application. here both the low current and low voltage noise of the AD745 can be taken advantage of, since it is desirable in some instances to have a large r f (which increases sensitivity to input current noise) and, at the same time, operate the amplifier at high noise gain. AD745 input source: photo diode, accelerometer, ect. r f c l c s r b i s figure 37. a model for an l-to-v converter in this circuit, the r f c s time constant limits the practical bandwidth over which flat response can be obtained, in fact: f b ? f c 2 p r f c s where: f b = signal bandwidth f c = gain bandwidth product of the amplifier with c l ? 1/(2 p r f c s ) the net response can be adjusted to a provide a two pole system with optimal flatness that has a corner frequency of f b . capacitor c l adjusts the damping of the circuits response. note that bandwidth and sensitivity are directly traded off against each other via the selection of r f . for example, a photodiode with c s = 300 pf and r f = 100 k w will have a maximum bandwidth of 360 khz when capacitor c l ? 4.5 pf. conversely, if only a 100 khz bandwidth were required, then the maximum value of r f would be 360 k w and that of capacitor c l still ? 4.5 pf. in either case, the AD745 provides impedance transformation, the effective transresistance, i.e., the i/v conversion gain, may be augmented with further gain. a wideband low noise amplifier such as the ad829 is recommended in this application. this principle can also be used to apply the AD745 in a high performance audio application. figure 38 shows that an i-v converter of a high performance dac, here the ad1862, can be designed to take advantage of the low voltage noise of the AD745 (2.9 nv/ ? hz ) as well as the high slew rate and bandwidth provided by decompensation. this circuit, with component values shown, has a 12 db/octave rolloff at 728 khz, with a passband ripple of less than 0.001 db and a phase deviation of less than 2 degrees @ 20 khz. 3 pole low pass filter 1 2 3 4 5 6 7 89 10 11 12 13 14 16 15 top view ad1862 20 bit d/a converter AD745 digital common digital inputs analog common 0.01 m f ?2v 0.01 m f +12v ?2v 0.01 m f 3k w 2000pf ?2v 10 m f + 100pf 0.1 m f 0.1 m f output +12v 0.01 m f + +12v 1 m f figure 38. a high performance audio dac circuit an important feature of this circuit is that high frequency energy, such as clock feedthrough, is shunted to common via a high quality capacitor and not the output stage of the amplifier, greatly reducing the error signal at the input of the amplifier and subsequent opportunities for intermodulation distortions. unbalanced balanced 2.9nv/ ? hz 10 100 1000 input capacitance ?pf 10 20 30 40 rti noise voltage nv/ ? hz 0 figure 39. rti noise voltage vs. input capacitance balancing source impedances as mentioned previously, it is good practice to balance the source impedances (both resistive and reactive) as seen by the inputs of the AD745. balancing the resistive components will optimize dc performance over temperature because balancing will mitigate the effects of any bias current errors. balancing input capacitance will minimize ac response errors due to the amplifiers input capacitance and, as shown in figure 39, noise performance will be optimized. figure 40 shows the required external components for noninverting (a) and inverting (b) configurations.
AD745 rev. c C12C c1507C24C2/91 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-pin plastic mini-dip (n) package 4 5 8 1 0 - 15 0.100 (2.54) typ seating plane 0.25 (6.35) 0.31 (7.87) 0.165 0.01 (4.19 0.25) 0.125 (3.18) min + - + - o.018 0.003 (0.46 0.08) + - + - 0.18 0.03 (4.57 0.76) 0.035 0.01 (0.89 0.25) + - + - 0.39 (9.91) max 0.30 (7.62) ref 0.011 0.003 (0.28 0.08) + - + - + - + - seating plane 0.292 (7.42) 0.300 (7.62) 0.419 (10.64) 0.394 (10.01) 0.104 (2.64) 0.003 (2.36) 0.011 (0.279) 0.004 (0.102) 0.413 (10.49) 0.396 (10.11) 0.019 (0.483) 0.014 (0.356) 0.060 (1.27) ref 0.0500 (1.27) 0.0157 (0.40) 0 - 8 9 16 18 see detail above 0.0125 (0.32) 0.0091 (0.23) 0.0291 (0.74) 0.0098 (0.25) x 45 16-pin soic (r) package 8-pin cerdip (q) package 0.005 (0.13) min 0.055 (1.35) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) max 0.320 (8.13) 0.290 (7.37) 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0 - 15 0.015 (0.38) 0.008 (0.20) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 4 1 5 8 AD745 output r 1 c b r b r 2 c s r s noninverting connection bs b s s 12 c = c r = r for r >> r or r AD745 output r b c s r s inverting connection r 1 c b c f c = c ii c r = r ii r bfs b1s figure 40. optional external components for balancing source impedances

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